ARCNET hub IP core for FPGA-based designs

Key Features

  • Fully compatible to ANSI/ATA 878.1 Local Area Network Standard for ARCNET
  • Variable number of ports (3, 5, 8 and more)
  • Automatic bit rate recognition and adaption
  • Supported bit rates adjustable from 156.25 kbit/s up to 10 Mbit/s
  • Two transmission modes: sine dipulse and backplane
  • ARCNET signal regeneration
  • Enhanced diagnostic features
  • Design entirely written in VHDL
  • May be easily adopted to other CPLD and FPGA types
  • Easy in-field updates and upgrades

Order information

Please contact us for the order and further information about this product.

Scope of application

The maximum length of a network segment is limited by the transfer method used when implementing ARCNET networks. Amplifiers (hubs) can connect several segments in series to expand networks. However, bit jitter and the regeneration of signal levels and signal shapes are important in this case. Although common hubs regenerate signal levels they do not reduce but even increase bit jitter.

In comparison to them the SH IP-CORE-ARCHUB regenerates signals and reduces bit jitter. With their very short transfer time of less than 3 bits, multiple SH IP-CORE-ARCHUB can be cascaded as long as the timeout conditions of connected ARCNET nodes are met.

Design & Functionality

The SH IP-CORE-ARCHUB is an ARCNET hub IP core that was designed for use in CPLDs and FPGAs. Due to use of VHDL, the design can be transferred easily to diverse CPLD and FPGA types from various manufactures such as Altera (MAX II, Cyclone and the Stratix series), and Xilinx (CoolRunner II, Spartan and Virtex series).

The IP core is completely compatible to ARCNET standards and can be used as replacement of SMSC Hub Controller TMC2005-xx. The SH IP-CORE-ARCHUB has already been used for long time in our market-proven product lines: SH ARC-Mx-HUB and SH ARC-HUB.

Diagnostic Features

The SH IP-CORE-ARCHUB can detect and report the multiple network events via LED's (see data sheet).